Error Detection Codes-2
Parity generator and checker network logic circuits constructed with exclusive-OR functions. This is because, as mentioned in Sec. 1·2, the exclusive-OR function of three or more varia.bles is by definition an odd function. An odd function is a logic function whose value is binary 1 if, and only if, an odd function number of variables are equal to 1. According to this definition, the P( even) is the exclusive-OR of x, y, and l because it is equal to 1 when either one or all three of the variables are equal to I (Table 3-7). The P(odd) function is the complement of the P(even) function.
These Topics Are Also In Your Syllabus | ||
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1 | Program Counter | link |
2 | Common Bus System | link |
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3 | Common Bus System-memory address | link |
4 | Computer Instructions | link |
5 | Instruction Set Completeness | link |
As an example, consider a 3-bit me&Sllge to be transmitted with an odd parity bit. At the sending end, the odd·parity bit is generated by a parity generator circuit. As shown in Fig. 3-3, this circuit consists of one exclusive-OR and one exclusive-NOR gate. Since P(even) is the exclusive-OR of x, y, z, and P(odd) is the complement of P(even), it is necessary to employ an exclusiveNOR gate for the needed complementation. The message and the odd-parity bit are transmitted to their destination where they are applied to a parity checker. An error has occurred during transmission if the parity of the four bits received is even, since the binary infonnation transmitted was originally odd. The output of the parity checker would be 1 when an error occurs, that is, when the number of l's in the four inputs is even. Since the exclusive-OR function of the four inputs is an odd function, we again need to complement the output by using an exclusive-NOR gate ..
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1 | ADD to AC | link |
2 | LDA: Load to AC | link |
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3 | STA: Store AC & BUN: Branch Unconditionally | link |
4 | BSA: Branch and Save Return Address | link |
5 | BSA: Branch and Save Return Address -subroutine call | link |
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1 | Shift Microoperations -arithmetic shift | link |
2 | Shift Microoperations -arithmetic shift | link |
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3 | Hardware Implementation- shift operator | link |
4 | Arithmetic Logic Shift Unit | link |
5 | Instruction Codes | link |
It is worth noting that the parity generator can use the same circuit as the parity checker if the fourth input is permanently held at a logic-Q value. The advantage of this is that the same circuit can be used for both parity generation and parity checking.
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1 | Register Transfer Language | link |
2 | Register Transfer Language -2 | link |
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3 | Register Transfer | link |
4 | Register Transfer -2 | link |
5 | Bus and Memory Transfers | link |
It is evident from the example above that even-parity generators and checkers can be implemented with exclusive-OR functions. Odd-parity networks need an exclusive-NOR at the output to complement the function.