Bus and Memory Transfers
Common bus:
A typical digital computer has many registers, and paths must be provided to transfer information from one register to another. The number of wires will be excessive if separate lines are used between each register and all other registers in the system.A more efficient scheme for transferring information between registers in a multiple-register configuration is a common bus system. A bus structure consists of a set of common lines, one for each bit of a register, through which binary information is transferred one at a time. Control signals determine which register is selected by the bus during each particular register transfer.
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1 | Fixed-Point Representation | link |
2 | Integer Representation | link |
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3 | Arithmetic Addition | link |
4 | ARITHMETIC SUBTRACTION | link |
5 | Overflow | link |
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1 | FLOW CONTROL | link |
2 | Decimal Fixed-Point Representation | link |
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3 | Floating-Point Representation | link |
4 | Floating-point representation | link |
5 | Other Binary Code | link |
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1 | Register Transfer | link |
2 | Register Transfer -2 | link |
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3 | Bus and Memory Transfers | link |
4 | Bus and Memory Transfers -2 | link |
5 | Three-State Bus Buffers | link |
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1 | Binary Adder-Subtractor | link |
2 | Binary lncrementer | link |
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3 | Logic Microoperations | link |
4 | List of Logic Microoperations | link |
5 | Hardware Implementation | link |
One way of constructing a common bus system is with multiplexers. The multiplexers select the source register whose binary information is then placed on the bus. The construction of a bus system for four registers is shown in Fig. 4-3. Each register has four bits, numbered 0 through 3. The bus consists of four 4 x 1 multiplexers each having four data inputs, 0 through 3, and two selection inputs, S1 and S0• In order not to complicate the diagram with 16 lines crossing each other, we use labels to show the connections from the outputs of the registers to the inputs of the multiplexers. For example, output 1 of register A is connected to input 0 of MUX 1 because this input is labeled A1. The diagram shows that the bits in the same significant position in each register are connected to the data inputs of one multiplexer to form one line of the bus. Thus MUX 0 multiplexes the four 0 bits of the registers, MUX 1 multiplexes the four 1 bits of the registers, and similarly for the other two bits.
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1 | Computer Instructions | link |
2 | Instruction Set Completeness | link |
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3 | Timing and Control | link |
4 | Timing and Control -2 | link |
5 | Instruction Cycle | link |