Timing and Control -2

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The last three waveforms in Fig. 5-7 show how SC is cleared when D3T4 = I. Output D3 from the operation decoder becomes active at the end of timing signal T2• When timing signal T4 becomes active, the output of the AND gate that implements the control function D3T4 becomes active. This signal is applied to the CLR input of SC. On the next positive clock transition (the one marked T, in the diagram) the counter is cleared to 0. This causes the timing signal To to become active instead of T5 that would have been active if SC were incremented instead of cleared.

until the memory word is available. To facilitate the presentation, we will assume that a wait period is not necessary in the basic computer.

T0: AR +-- PC

specifies a transfer of the content of PC into AR if timing signal To is active. T0 is active during an entire clock cycle intervaL During this time the content of PC is placed onto the bus (with 525150 = 010) and the LD (load) input of AR is enabled. The actual transfer does not occur until the end of the clock cycle when the clock goes through a positive transition. This same positive clock transition increments the sequence counter SC from 0000 to 0001 . The next clock cycle has T1 active and T0 inactive.


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1 Other Alphanumeric Codes link
2 Error Detection Codes link
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3 Error Detection Codes-2 link
4 Register Transfer Language link
5 Register Transfer Language -2 link

Rating - 3/5

Rating - 3/5