AND to AC
This is an instruction that performs the AND logic operation on pairs of bits in AC and the memory word specified by the effective address. The result of the operation is transferred to AC. The rnicrooperations that execute this instruction are:
D0T4: DR <-M[AR]
D0T5: AC <- AC /\ DR, SC <--- 0
The control function for this instruction uses the operation decoder D0 since this output of the decoder is active when the instruction has an AND operation whose binary code value is 000. Two timing signals are needed to execute the instruction. The clock transition associated with timing signal T4 transfers the operand from memory into DR. The clock transition associated with the next timing signal T5 transfers to AC the result of the AND logic operation between the contents of DR and AC. The same clock transition clears SC to 0, transferring control to timing signal T0 to start a new instruction cycle.
Frequently Asked Questions
+
Ans: In order to specify the rnicrooperations needed for the execution of each
instruction, it is necessary that the function that they are intended to perform
be defined precisely. Looking back to Table 5-2, where the instructions are
listed, we find that some instructions have an ambiguous description. This is
because the explanation of an instruction in words is usually lengthy, and not
enough space is available in the table for such a lengthy explanation. We will
now show that the function of the memory-reference instructions can be
defined precisely by means of register transfer notation. view more..
+
Ans: Register-reference instructions are recognized by the control when 07 = 1 and
I = 0. These instructions use bits 0 through 11 of the instruction code to specify
one of 12 instructions. These 12 bits are available in IR(0-11). They were also
transferred to AR during time T2• view more..
+
Ans: The timing signal that is active after the decoding is T3• During time T,, the
control unit determines the type of instruction that was just read from memory.
The flowchart of Fig. 5-9 presents an initial configuration for the instruction
cycle and shows how the control determines the instruction type after the
decoding. The three possible instruction types available in the basic computer
are specified in Fig. 5-5. view more..
+
Ans: This is an instruction that performs the AND logic operation on pairs of bits
in AC and the memory word specified by the effective address. The result of view more..
+
Ans: This instruction adds the content of the memory word specified by the effective
address to the value of AC. The sum is transferred into AC and the output carry
C,., is transferred to the E (extended accumulator) flip-flop. The rnicrooperations
needed to execute this instruction are view more..
+
Ans: This instruction transfers the memory word specified by the effective address
to AC. The rnicrooperations needed to execute this instruction are
view more..
+
Ans: This instruction stores the content of AC into the memory word specified by
the effective address. Since the output of AC is applied to the bus and the data
input of memory is connected to the bus, we can execute this instruction with
one microoperation: view more..
+
Ans: This instruction is useful for branching to a portion of the program called a
subroutine or procedure. When executed, the BSA instruction stores the address
of the next instruction in sequence (which is available in PC) into a
memory location specified by the effective address. The effective address plus
one is then transferred to PC to serve as the address of the first instruction in
the subroutine. This operation was specified in Table 5-4 with the following
register transfer: view more..
+
Ans: The BSA instruction performs the function usually referred to as a subroutine
call. The indirect BUN instruction at the end of the subroutine performs
the function referred to as a subroutine return. In most commercial computers,
the return address associated with a subroutine is stored in either a processor view more..
+
Ans: This instruction increments the word specified by the effective address, and
if the incremented value is equal to 0, PC is incremented by 1. The programmer
usually stores a negative number (in 2's complement) in the memory word. As
this negative number is repeatedly incremented by one, it eventually reaches
the value of zero. At that time PC is incremented by one in order to skip the
next instruction in the program. view more..
+
Ans: A computer can serve no useful purpose unless it communicates with the
external environment. Instructions and data stored in memory must come
from some input device. Computational results must be transmitted to the user
through some output device. Commercial computers include many types of view more..
+
Ans: The input register INPR consists of eight bits and holds an alphanumeric
input information. The 1-bit input flag FGI is a control flip-flop. The flag bit is view more..
+
Ans: The final flowchart of the instruction cycle, including the interrupt cycle for the
basic computer, is shown in Fig. 5-15. The interrupt flip-flop R may be set at
any time during the indirect or execute phases. Control returns to timing signal
T0 after SC is cleared to 0. If R = 1, the computer goes through an interrupt
cycle. If R = 0, the computer goes through an instruction cycle. view more..
+
Ans: 1. A memory unit with 4096 words of 16 bits each
2. Nine registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
3. Seven flip-flops: I, S, E, R, lEN, FGI, and FGO
4. Two decoders: a 3 x 8 operation decoder and a 4 x 16 timing decoder view more..
+
Ans: he block diagram of the control logic gates is shown in Fig. 5-6. The inputs
to this circuit come from the two decoders, the I flip-flop, and bits 0 through
11 of IR. The other inputs to the control logic are: AC bits 0 through 15 to check
if AC = 0 and to detect the sign bit in AC( view more..
+
Ans: The registers of the computer connected to a common bus system are shown
in Fig. 5-4. The control inputs of the registers are LD (load), INR (increment),
and CLR (clear). Suppose that we want to derive the gate structure associated
with the control inputs of AR. We scan Table 5-6 to find all the statements that
change the content of AR view more..
+
Ans: The control gates for the seven flip-flops can be determined in a similar
manner. For example, Table 5-6 shows that lEN may change as a result of the
two instructions ION and !OF. view more..
+
Ans: The 16-bit common bus shown in Fig. 5-4 is controlled by the selection inputs
S2, S1, and 50• The decimal number shown with each bus input specifies the
equivalent binary number that must be applied to the selection inputs in order
to select the corresponding register. Table 5-7 specifies the binary numbers for
S2S1S0 that select each register. Each binary number is associated with a Boolean
variable x1 through x7, corresponding to the gate structure that must be active
in order to select the register or memory for the bus. view more..
Recommended Posts:
- DATA TYPES
- NUMBER SYSTEM
- CONVERSION - INTRODUCTION
- OCTAL AND HEXADECIMAL NUMBER CONVERSION
- OCTAL AND HEXADECIMAL NUMBER CONVERSION -2
- Introduction to Decimal Representation
- ALPHANUMERIC REPRESENTATION
- Complements
- Complements -2
- Subtraction of Unsigned Numbers
- Subtraction of Unsigned Numbers-2
- Fixed-Point Representation
- Integer Representation
- Arithmetic Addition
- ARITHMETIC SUBTRACTION
Rating - 3/5
Advertisements