Input - output Register




The input register INPR consists of eight bits and holds an alphanumeric input information. The 1-bit input flag FGI is a control flip-flop. The flag bit is set to 1 when new information is available in the input device and is cleared to 0 when the information is accepted by the computer. The flag is needed to synchronize the timing rate difference between the input device and the computer. The process of information transfer is as follows. Initially, the input flag FGI is cleared to 0. When a key is struck in the keyboard, an 8-bit alphanumeric code is shifted into INPR and the input flag FGI is set to 1. As long as the flag is set, the information in INPR cannot be changed by striking another key. The computer checks the flag bit; if it is 1, the information from INPR is transferred in parallel into AC and FGI is cleared to 0. Once the flag is cleared, new information can be shifted into INPR by striking another key.

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Register Transfer Language Timing And Control -2
Shift Micro-operations - Logical, Circular, Arithmetic Shifts Instruction Cycle
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Computer Instructions Sta: Store Ac & Bun: Branch Unconditionally

The output register OUTR works similarly but the direction of information flow is reversed. Initially, the output flag FGO is set to 1. The computer checks the flag bit; if it is 1, the information from AC is transferred in parallel to OUTR and FGO is cleared to 0. The output device accepts the coded information, prints the corresponding character, and when the operation is completed, it sets FGO to 1. The computer does not load a new character into OUTR when FGO is 0 because this condition indicates that the output device is in the process of printing the character.

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Subtraction Of Unsigned Numbers Shift Micro-operations - Logical, Circular, Arithmetic Shifts
Fixed-point Representation Instruction Codes
Bus And Memory Transfers -2 Indirect Address
List Of Logic Microoperations Add To Ac
Hardware Implementation Lda: Load To Ac


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