Control of Registers and Memory



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The registers of the computer connected to a common bus system are shown in Fig. 5-4. The control inputs of the registers are LD (load), INR (increment), and CLR (clear). Suppose that we want to derive the gate structure associated with the control inputs of AR. We scan Table 5-6 to find all the statements that change the content of AR

R 'T0: AR +- PC

R'T2: AR +-IR(0-1 1)

D7IT3: AR +-M[AR]

RT0: AR +-0 D5T4: AR +-AR + 1

The first three statements specify transfer of information from a register or memory to AR . The content of the source register or memory is placed on

the bus and the content of the bus is transferred into AR by enabling its LD control input. The fourth statement clears AR to 0. The last statement increments AR by 1. The control functions can be combined into three Boolean expressions as follows:

LD(AR) = R'To + R'T, + D;

IT, CLR(AR) = RTo

INR(AR) = D5T,

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where LD(AR) is the load input of AR, CLR(AR) is the clear input of AR, and INR(AR) is the increment input of AR . The control gate logic associated with AR is shown in Fig. 5-16.

Control of Registers and Memory


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